1. Field of the Invention
The present invention relates to an internal clock signal generation circuit and a synchronous type semiconductor memory device. More particularly, the present invention relates to an internal clock signal generation circuit that generates an internal clock signal synchronizing in phase with an external clock signal, and a synchronous type semiconductor memory device that accepts an external signal in synchronization with a clock signal provided periodically from an internal clock signal generation circuit.
2. Description of the Background Art
Although the operating speed of a dynamic access memory (referred to as DRAM hereinafter) employed as a main memory has been increased, it has not necessarily come to the level of the operating speed of a microprocessor (referred to as MPU hereinafter) yet.
Therefore, the performance of the entire system is degraded on account of the bottleneck of the access time and cycle time of the DRAM.
In recent years, a synchronous DRAM (referred to as SDRAM hereinafter) operating in synchronization with a clock signal is proposed as a main memory corresponding to a high speed MPU. Such an SDRAM will be described hereinafter.
Referring to FIG. 17, a conventional SDRAM 100 includes a clock buffer 101, a control signal buffer 102, an address buffer 103, a control circuit 104, a memory array 105, and an input/output buffer 106.
Memory array 105 includes a plurality of memory cells (not shown) connected in a matrix of rows and columns. Clock buffer 101 outputs a clock signal CLK for an internal operation according to an external clock signal ext.CLK. Control signal buffer 102 receives various control signals for driving control circuit 104 such as a /RAS signal (row address strobe signal), a /CAS signal (column address strobe signal), and a /WE signal (write enable signal). Address buffer 103 receives an address signal Add designating a memory cell to be selected from address pins A0-A10. Control circuit 104 renders a memory cell to a selected state in synchronization with clock signal CLK. Input/output buffer 106 responds to clock signal CLK to receive data to be written to the selected memory cell or output data read out from the selected memory cell via data input/output terminals DQ0-DQ7. SDRAM 100 inputs/outputs a byte of 8 bits from data input/output terminals DQ0-DQ7.
The operation of SDRAM 100 will be described hereinafter. In SDRAM 100, a (high speed access) specification is proposed for outputting or inputting data of a plurality of bits continuously from one data input/output terminal in synchronization with a system clock.
Referring to FIG. 18, SDRAM 100 receives an externally applied /RAS signal, /CAS signal, address signal Add, and the like at a rising edge of an external clock signal ext.CLK which is a system clock.
Address signal Add has a row address signal X and a column address signal Y applied in a time-divisionally multiplexed manner. When /RAS signal is at an active state (L level=logical low) at a rising edge of external clock signal ext.CLK, address signal Add is entered as a row address signal X (for example, Xa in FIG. 18).
Then, when /CAS signal is at an active state (L level) at a rising edge of external clock signal ext.CLK, address signal Add is entered as a column address signal Y (for example, Yb in FIG. 18).
Row and column selection is effected according to such entered row and column address signals Xa and Yb.
At an elapse of a predetermined clock period (six clock cycles in FIG. 18) from the fall of /RAS signal to an L level, the first 8 bits of data (q0) is output. Subsequently, data (q1-q7) is output in response to the rise of external clock signal ext.CLK.
In a write operation, row address signal X (Xc in FIG. 19) is entered according to a procedure similar to that of a read out operation as shown in FIG. 19. When /CAS signal and /WE signal both are at an active state (L level) at the rising edge of external clock signal ext.CLK, column address signal Y (Yd in FIG. 19) is entered and the input data d0 applied at that time is entered as the first write data. In response to the fall of signals /RAS and /CAS, the select operation of a row and column is effected. Input data d1-d7 are sequentially entered in synchronization with external clock signal ext.CLK to be written into a relevant memory cell.
In SDRAM 100, /RAS signal, /CAS signal, address signal Add and input data are entered at a rising edge of external clock signal ext.CLK which is a system clock, in contrast to the conventional method of a DRAM receiving an address signal Add and input data in synchronization with control signals (signals /RAS and /CAS).
The structure of operating in synchronization with an external clock signal is advantageous in that the margin for the data input/output time caused by the skew (deviation in timing) of address signal Add does not have to be ensured, so that the cycle time can be reduced. The continuous access time can be speeded if writing/reading of continuous data can be carried out in synchronization with a clock signal.
In a SDRAM, an internal clock signal CLK that drives the internal operation must be speeded in order to realize high speed operation. The art of incorporating a delay locked loop (referred to as DLL hereinafter) in the chip is proposed aimed to generate an internal clock signal int.CLK having a rising phase ahead of external clock signal ext.CLK.
Referring to FIG. 20, a conventional DLL circuit 90 includes a delay line 91, a clock buffer 93, a phase comparator 94, a select circuit 92, and a delay circuit 95.
DLL circuit 90 is a digital type DLL circuit that can suppress the power noise more than an analog type DLL circuit.
Clock buffer 93 outputs a clock signal ECLK according to external clock signal ext.CLK. Delay line 91 delays the input clock signal ECLK to provide an internal clock signal int.CLK. Internal clock signal int.CLK is delayed by delay circuit 95 to be provided to phase comparator 94 as a clock signal RCLK. Phase comparator 94 compares the phases between clock signals ECLK and RCLK to provide an up signal UP and a down signal DOWN so that the phases substantially match each other (synchronization established). Select circuit 92 is formed of a shift register to vary the delay time of delay line 91 according to up and down signals UP and DOWN. SDRAM 100 of FIG. 17 operates according to internal clock signal int.CLK.
Referring to FIG. 21, delay line 91 includes a plurality of NAND circuits (110.1, 110.2, . . . 110.n) and a plurality of inverter circuits (111.1, 111.2, . . . , 111.n) connected alternately, and a plurality of NAND circuits (112.1, 112.2, . . . 112.n) connected to respective input terminals of NAND circuits (110.1, 110.2, . . . , 110.n).
NAND circuit 110.1 has one input terminal connected to an internal power supply voltage Vcc. Internal clock signal int.CLK is output from inverter circuit 111.n.
The plurality of NAND circuits (112.1. 112.2, 112n) have respective one input terminals receive clock signal ECLK and the other respective input terminals receive control signals (s(1), s(2), . . . , s(n)) output from select circuit 92.
Any one of the control signals (s(1), s(2), s(n)) output from select circuit 92 is at an active state. The position where clock signal ECLK is input (more specifically, which of NAND circuits 110.1, . . . , 110.n the signal passes) depends upon the control signal (s(1), s(2), . . . , s(n)).
For the sake of simplification, the direction of s(1) is referred to as the first stage side and the direction of s(n) is referred to as the subsequent stage side in the series of the control signals (s(1), s(2), . . . , s(n)). When the delay period is too long, any of control signals S(j+1), . . . , s(n) of the subsequent stage side is activated instead of the current active control signal s(j). When the delay period is too short, any of control signals s(j-1), . . . , s(1) of the first stage side is activated instead of the active control signal s(j). Thus, the delay period of delay line 91 varies.
In a conventional DLL circuit 90 of the above-described structure, the step of change in the delay time depends upon NAND circuits (110.1, . . . , 110.n) and inverter circuits (111.1, . . . , 111.n).
There was a problem in the conventional DLL circuit 90 that phase synchronization cannot be established if the operating frequency of an input signal (for example, external clock signal ext.CLK) becomes too great since the delay time is varied in a step-like manner.
Furthermore, a high speed access operation cannot be realized with a SDRAM incorporating such a DLL circuit 90.